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[Other] iir_par_code

Description: IIR code. IEEE STD 1364-1995 Verilog file: iir_par.v.
Platform: | Size: 1024 | Author: 无名 | Hits:

[VHDL-FPGA-Verilog] FPGAREAL

Description: 信号处理FPGA实现参考,IEEE transaction 的一篇文章。主要针对信号处理中加窗、FFT、VSLI快速实现中误差地等问题。-FPGA realization of a reference signal processing, IEEE transaction of an article. Mainly for signal processing windowing, FFT, VSLI rapid error problems.
Platform: | Size: 308224 | Author: 卓智海 | Hits:

[Other] alu_Verilog

Description: It is the code for implementing the project titled "The Reconfigurable Instruction Cell Array(IEEE 2008)".
Platform: | Size: 5120 | Author: masth | Hits:

[Program doc] xge_mac_latest.tar

Description: Language - Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. -Language- Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae.
Platform: | Size: 813056 | Author: Maxim | Hits:

[Other] SamilPalnitkar

Description: Verilog HDL A Guide to Digital Design and Synthesis, Second edition IEEE 1364-2001 compliant by Samir Palnitkar. This book will definitely going to be very useful for the beginners as the contents of it are well explained with proper examples and illustrations. The author starts the language from very scratch to professional level.
Platform: | Size: 1723392 | Author: rksant | Hits:

[Other] verilog-ieee

Description: verilog 2001 LRM.IEEE standard.
Platform: | Size: 2181120 | Author: muylor | Hits:

[RFID] 2

Description: RFID系统的IEEE的文章，安全协议，认证- In this paper, we first propose a cryptographic authentication protocol which meets the privacy protection for tag bearers, and then a digital Codec for RFID tag is designed based on the protocol. The protocol which uses cryptographic hash algorithm is based on a three-way challenge response authentication scheme. In addition, we will show how the three different types of protocol frame formats are formed by extending the ISO/IEC 18000-3 standard[3] for implementing the proposed authentication protocol in RFID system environment. The system has been described in Verilog HDL and also synthesized using Synopsys Design Compiler with Hynix 0.25 µ m standard-cell library. From implementation results, we found that the proposed scheme is well suite to implement robust RFID system against active attacks such as the man-in-the-middle attack.
Platform: | Size: 233472 | Author: fxy | Hits:

[VHDL-FPGA-Verilog] fpu100_latest.tar

Description: 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in hardware and software.
Platform: | Size: 1981440 | Author: 赵恒 | Hits:

[Software Engineering] verilog-ieee

Description: verilog introduction
Platform: | Size: 2174976 | Author: Nguyen Trong Tri | Hits:

[VHDL-FPGA-Verilog] ofdm

Description: ofdm调制解调的fpga实现。使用Verilog实现IEEE 802.16a系统的调制解调模块。-ofdm modulation and demodulation of fpga implementation. Verilog implementation using IEEE 802.16a system, modem module.
Platform: | Size: 2048 | Author: 张维 | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] emiraga-ieee754-verilog-b7a63aa

Description: IEEE 754 floating point
Platform: | Size: 17408 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] Introduction-to-Verilog

Description: Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, -Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, Verilog 1364
Platform: | Size: 191488 | Author: zhujizhen | Hits:

[VHDL-FPGA-Verilog] IEEE-standard-Verilog-HDL1364-2001

Description: verilog 硬件描述语言 golden版-verilog hardware descriptor language golden version
Platform: | Size: 2186240 | Author: willow | Hits:

[VHDL-FPGA-Verilog] verilog-RTLevel-Synthesis

Description: 本章详细的分析了寄存器传输级综合，ieee最新标准-IEEE Standard for Verilog® Register Transfer Level Synthesis
Platform: | Size: 380928 | Author: 王凯 | Hits:

[VHDL-FPGA-Verilog] Perl_for_CRC

Description: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
Platform: | Size: 90112 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] IEEE-standard-Verilog-HDL

Description: IEEE 标准 Verilog 硬件描述语言，这是IEEE 制订的verilog 标准参考文档-IEEE Standard for Verilog Hardware Description Language
Platform: | Size: 3170304 | Author: 唐小飞 | Hits:

[Software Engineering] Verilog-IEEE-Std(1364-2005)

Description: Verilog IEEE Std(1364-2005) 标准,硬件开发必备手册-Verilog IEEE Std (1364-2005) standards, hardware development of the necessary manual
Platform: | Size: 3174400 | Author: panqihe | Hits:

[Other] 2005-Verilog-IEEE-Std(1364-2005)

Description: IEEE Standard for Verilog Hardware Description Language 1364-2005 verilog2005版本的标准-IEEE Standard for Verilog Hardware Description Language 1364-2005
Platform: | Size: 3185664 | Author: 赵先生 | Hits:

[VHDL-FPGA-Verilog] Prentice---Verilog.HDL_A.Guide.to.Digital.Design.

Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.-Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Platform: | Size: 1723392 | Author: bom | Hits:
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